Transistors forksheet: the key to scaling beyond 2 nm

The semiconductor industry is experiencing a pivotal moment: Transistor forksheets have crept into all roadmaps Leading manufacturers see this as the next big step forward for scaling beyond traditional GAA nanosheets. And it's no coincidence: each new node is more expensive, more complex, and more delicate, so any architecture that squeezes more density, performance, and efficiency without skyrocketing costs automatically becomes a key player.

Within this panorama, Samsung, Intel, TSMC, and imec are moving at full speed to define what the 2 nm, 1 nm, and future angstrom generations (A14, A10, A7, etc.) nodes will be like. In this process, the forksheet is destined to be a "smart intermediate step" between current nanosheet GAAs and future CFETs (Complementary FETs), which will arrive when the vertical integration of nanop devices stacked on top of each other becomes an industrial reality and not just a laboratory exercise.

What is a transistor forksheet and why does it matter so much?

The forksheet transistor is a direct evolution of the GAA nanosheet transistor.Designed to maximize logic and SRAM density without requiring a complete redesign of the manufacturing process, the key lies in introducing a strategic dielectric wall that allows nMOS and pMOS transistors to be placed much closer together without triggering parasitic capacitance.

In conventional GAA nanosheets, The limitation comes not so much from the channel itself as from the distance between the complementary devices. which form a CMOS logic gate. If they are placed too close together, the capacitance between N/P areas increases dramatically, degrading performance, increasing power consumption, and contaminating the signal. This minimum distance was becoming a real bottleneck for further reducing the size of standard cells.

Imec, which has been leading the way in advanced device research for years, began to study where the scalability of nanosheets started to "break down". The result of those studies was the idea of ​​the forksheetInstead of leaving the space between complementary transistors "exposed," an insulating wall is introduced that physically separates zones of devices of the same type, depending on the variant.

In its original conception, The forksheet placed an internal dielectric wall between the nMOS and the pMOS within the same standard cell. This wall allows the two transistors to be placed even closer together without significantly increasing capacitance, because it acts as an electrical barrier between the gates and the active regions. Thus, the designer faces two options: reduce the cell area to fit more logic per square millimeter or use the "extra" space to widen the nanosheets and gain performance.

The numbers that the industry deals with are not insignificant: According to simulations, compared to a classic GAA nanosheetA forksheet design can achieve up to 10% higher performance, an improvement of around 24% in energy efficiency, and a reduction in cell area of ​​nearly 20%. All this while maintaining a large part of the process steps already mastered for nanosheets.

From FinFET to GAA and from GAA to forksheet: the next step

To understand where the forksheet fits in, we need to look back for a moment. When FinFETs came to market, they solved the channel control problem. that planar transistors suffered as the node shrank. The "fin" or fin raised the channel in 3D and the gate embraced three sides, improving electrostatic control and reducing leakage.

The next leap has been the gate-all-around (GAA), where The channel is no longer a fin but several stacked horizontal silicon sheetscompletely surrounded by the gate. This further strengthens channel control and allows scaling to 3nm, 2nm, and beyond. Intel, TSMC, and Samsung are in the midst of transitioning to this architecture with their Intel 18A, TSMC N2, and Samsung SF3E nodes, among others.

However, even GAA with nanosheets has an expiration date. The great aspiration of the logic industry is the CFETwhere the nyp transistors are stacked vertically on top of each other, so that, at the plant level, they occupy the footprint of a single device. This could practically halve the area of ​​certain critical cells and provide massive improvements in density and PPA (power, performance, area).

The problem is that CFET is a real integration nightmare.It requires precise material control and extremely accurate alignment between stacked devices, as well as a very delicate process choreography to avoid damaging the transistors below while manufacturing those above. This is why imec and other players consider the forksheet a reasonable intermediate step: it reuses most of the GAA flux, adds a dielectric wall, and improves density without yet making the leap to full vertical stacking.

From a temporal perspective, IMEC positions the forksheet as the main focus towards the end of this decade, with a view to production around 2028, while the high-end CFET would be more likely to be ready in the early-mid 30s, with industrial production maturity around 2032 according to their estimates.

Samsung's vision: forksheet to reach 1nm

Samsung Foundry is no longer limited to competing node by node with TSMC or chasing Intel's timeline; The Koreans have clearly set their sights on the 1 nm node by around 2031, and the forksheet is a central part of its strategy. The company wants to focus heavily on density, efficiency, and performance, even though TSMC will continue to lead in volume.

In this plan, Samsung plans to use transistors with channel widths close to 1 nmwhich is equivalent to about five atoms. This is not just an incremental reduction from 2 nm, but a true current physical frontier with respect to channel control, materials handling, and device-to-device statistical variability.

Samsung's forksheet approach seeks minimize the space between transistors Taking advantage of the limitations of current lithographic scanners, an insulating "wall" is introduced between devices to contain the electrical interaction between them, further increasing the density per unit area. Less physical separation means more transistors in the same space, but also greater demands on leakage and coupling control; this is why the dielectric wall is critical.

Until now, the leap from FinFET to GAA had already allowed a notable improvement in energy efficiencyThe channel, surrounded on four sides, reduces leakage compared to the three-sided gate of FinFETs. The forksheet adds further optimization by addressing one of the major bottlenecks: the physical distance between nyp devices within the cell. To scale beyond 2 nm without compromising power consumption or performance, these kinds of aggressive solutions become essential.

In the market context, Samsung remains the second major player in foundry operations. In terms of volume, TSMC operates in a different league with over 70% of the global market share. Even so, the Koreans have skillfully leveraged timely innovation: they were the first to introduce EUV in their 7nm node and also the first to put GAA into production at 3nm. This hasn't given them revenue leadership, but it has ensured a consistent presence in the technology conversation.

The 1 nm node with forksheet should be viewed, for now, as a sign of territory and technological ambition Rather than seeing it as something that will immediately flood the market, the real challenge will be transforming that theoretical advantage in density and PPP into actual production with reasonable yields and affordable costs. That's where, historically, the true winners are decided: not at conference presentations, but in the factory.

Inner wall and outer wall: the evolution of forksheet design

When imec presented the forksheet concept in 2017, The original architecture was based on an “inner wall” Located between the nMOS and pMOS devices within the standard cell, the insulating wall was introduced early in the flow, before the gate pattern, and from then on had to survive countless processing steps: selective etching, deposition of different dielectrics, heat treatments, etc.

This approach presented several significant difficulties. The width of that wall had to be extremely smallon the order of 8 to 10 nm, if a cell height of around 90 nm was to be maintained. With such a thin wall exposed to so many subsequent steps, any slight over-etch or chemical attack could erode it uncontrollably. This imposed very strict requirements on the dielectric material and the process tolerances.

Furthermore, In many logic designs, the gates of the np transistors share part of the trace.By placing a rigid barrier between them, this connection becomes complicated: either the door has to "jump" over the wall, which adds unwanted parasitic capacitance, or more unusual routing solutions are needed that end up penalizing performance and area.

Another sensitive point of the inner wall forksheet was the channel control. The geometry of the gate in the initial implementation only really embraced three sides of the channelTherefore, electrostatic control was not as good as that of a textbook GAA. As channel lengths continue to decrease, this relative loss of control becomes increasingly problematic.

Faced with these limitations, imec has taken a new approach with a new variant called “outer wall forksheet”In this version, the insulating wall is now located at the edge of the standard cell, separating devices of the same type belonging to adjacent cells, instead of inserting the barrier within the cell itself between the nMOS and the pMOS. This significantly changes the integration approach.

When drafting the wall towards the outside, Its width can be increased to about 15 nm without penalizing the overall height of the cell.This allows it to be built with well-known materials and tools, such as silicon dioxide, and, above all, to be introduced later in the manufacturing sequence, once critical steps such as source/drain formation or nanosheet release have been completed. By entering the flow later, the wall is exposed to fewer aggressive processes, making it easier to maintain its integrity.

Advantages of the outer wall forksheet: better control and easier manufacturing

Relocating the wall on the outer wall forksheet not only improves manufacturability, It also simplifies the integration of the transistor gate.Now the gate can be extended continuously over the nyp devices without having to cross a barrier in the middle of the cell, reducing routing complexity and avoiding adding unnecessary parasitic capacitance.

Another interesting trick of the outer wall forksheet is to trim the wall slightly at the end of the processIf, in the final steps, approximately 5 nm of that wall are removed, the gate can wrap around a larger portion of the channel, recovering and even improving electrostatic control compared to the previous variant. Simulations presented by imec indicate an increase of around 25% in conduction current thanks to this improvement in gate-channel coupling.

The new design also solves a classic problem of nanosheets and the first generation of forksheets: the continuity of mechanical stress (strain) in the channelDuring the process, a protective mask covers the area where the outer wall will later form, so the silicon beneath the mask remains a continuous crystalline block. This allows strain-inducing source/drain materials—for example, silicon-germanium for pMOS—to transmit strain more efficiently to the channel.

In previous architectures, with vertical interruptions and discontinuities, That mechanical effort was diminished by misalignments and defectsThe result was reduced carrier mobility and, therefore, less current for the same voltage. The outer wall forksheet largely avoids these problems, allowing for a more uniform and systematic application of strain.

Simulations in SRAM memories and oscillators confirm that at node A10 (around 1 nm / 10 angstroms), the new arrangement can achieve a cell area reduction of approximately 22% compared to nanosheet-based A14 designs, taking advantage of a tighter gate pitch and denser packing of similar devices. In oscillator circuits, when full strain is applied, the outer wall forksheet performance matches or exceeds that of equivalent A14 and 2 nm designs; without strain, the conduction current drops by approximately 33%, highlighting the criticality of this factor.

Beyond the specific figures, The great advantage of the outer wall forksheet is that it recycles a good part of the know-how of nanosheetIt uses familiar materials, existing equipment in current factories, and process sequences that don't require rebuilding the entire plant. This reduces risk, costs, and maturation time compared to more disruptive alternatives.

Metrology challenges and defects in forksheet structures

As transistor structures become smaller and more intricate, Defect detection is becoming an increasingly major headacheIn next-generation CMOS, the challenge is no longer just "making the transistor," but being able to see and accurately measure minute structural defects that nevertheless have a huge impact on electrical behavior.

In the case of forksheet FETs, although density, performance, and theoretical efficiency are gained.The absolute size of typical defects (line roughness, pitch deviations, curvatures, profile asymmetries, etc.) does not decrease in the same proportion as the nominal dimensions of the device. This means that any small anomaly occupies, in relative terms, an increasingly larger portion of the transistor, with more pronounced effects.

In this context, Classical metrology techniques fall short to adequately characterize these new architectures. Within the European IT2 project, the company Semilab and its experts in spectroscopic ellipsometry have developed generalized ellipsometry methods and, in particular, have explored the use of Mueller Matrix Ellipsometry to detect structural asymmetries in forksheet FET arrays.

The idea goes through simulate Mueller matrix measurements under different degrees and directions of asymmetries In the forksheet profile: subtle variations in wall slope, differences between branches, small bends, or misalignments. From these simulations, the extent to which the optical responses associated with each type of defect can be distinguished from one another is quantified, and the correlation between asymmetry parameters is calculated.

A critical factor in this type of advanced optical measurement is the precise alignment of the sampleA slight error in positioning can mask or mimic certain asymmetries, so part of the work focuses on understanding how alignment uncertainty affects measurements and on designing methods to filter or compensate for it.

These types of developments are fundamental for European industry, which seeks to strengthen its role as a relevant technological player in semiconductorsBeyond manufacturing the most advanced nodes, projects like this provide characterization tools and process knowledge that allow for refining the manufacturing and improving the performance of increasingly complex devices, including forksheets.

Forksheet as a bridge to CFETs and the future beyond 2 nm

The leading logic manufacturers agree that Nanosheet-based GAA cannot be stretched indefinitely. beyond a few generations. As the nodes get smaller—2 nm, A14, A10, and whatever comes next—the levers of purely geometric scaling are exhausted, and more radical architectural changes are needed; demands such as the quantum computing They are an example of why new routes of density and performance are being sought.

In that scenario, CFET appears as the “ultimate CMOS architecture” In the long term, according to experts at IMEC, stacking a N and a P transistor vertically drastically reduces the area of ​​certain logic and memory blocks, increasing density without having to push the lateral pitch to impractical limits.

But, as already mentioned, CFET's integration is enormously complexInterfaces, tensions, alignments, and process steps must be controlled with a level of precision far exceeding what is currently routine. Therefore, the industry needs a gradual transition that allows it to learn, in production, how to manage hybrid structures and critical dielectric walls without relying entirely on a still-emerging technology.

The forksheets, and in particular the outer wall variant, fit right into this gap. Many of the manufacturing lessons learned from producing forksheets in high volume They will be reusable for CFETs: from the handling of thin insulating walls, to strain control, to the integration of shared gates and the management of defects in very high density environments.

IMC places the outer wall forksheet as key architecture to extend the nanosheet era to the A10 nodeWhile CFET is maturing and will be introduced on a large scale later in the 2030s, in practice this means that for several nodes we will see architectures coexist and overlap: early forksheets in production, CFET in pilot lines, "classic" GAA still in large volumes for markets that do not need the very latest technology, etc.

It is also being discussed what type of transistors to place on each side of the wall in the different forksheet versions. The original idea put nMOS on one side and pMOS on the other, like in a classic CMOS. However, configurations are being considered that place devices of the same type on both sides to optimize certain cells or improve critical paths, depending on the design needs and the type of circuit (logic, SRAM, oscillators, etc.). To this day, this choice remains an open field of research and optimization.

Looking ahead to the coming years, The sector's commitment is clear.Use a forksheet to keep the escalation of density and performance alive with incremental investment in process, and reserve the most dramatic leap for when CFETs are truly ready and manufacturing and metrology tools can support it without sinking yields.

All this movement surrounding transistor forksheets suggests that, although physics imposes hard limits, There is still room to further tighten the nodes below 2 nmThe combination of well-designed dielectric walls, strain control, new metrology schemes, and a gradual evolution towards vertical architectures opens a window of opportunity for manufacturers like Samsung, along with reference centers like imec, to continue setting the technological pace for the next decade, provided they can transform these ideas into stable and profitable production lines.